1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to methods of using adaptive sampling techniques based upon categorization of process variations, and a system for performing same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
By way of background, an illustrative field effect transistor 10, as shown in FIG. 1, may be formed above a surface 15 of a semiconducting substrate or wafer 11 comprised of doped-silicon. The substrate 11 may be doped with either N-type or P-type dopant materials. The transistor 10 may have a doped polycrystalline silicon (polysilicon) gate electrode 14 formed above a gate insulation layer 16. The gate electrode 14 and the gate insulation layer 16 may be separated from doped source/drain regions 22 of the transistor 10 by a dielectric sidewall spacer 20. The source/drain regions 22 for the transistor 10 may be formed by performing one or more ion implantation processes to introduce dopant atoms, e.g., arsenic or phosphorous for NMOS devices, boron for PMOS devices, into the substrate 11. Shallow trench isolation regions 18 may be provided to isolate the transistor 10 electrically from neighboring semiconductor devices, such as other transistors (not shown). Additionally, although not depicted in FIG. 1, a typical integrated circuit device is comprised of a plurality of conductive interconnections, such as conductive lines and conductive contacts or vias, positioned in multiple layers of insulating material formed above the substrate. These conductive interconnections allow electrical signals to propagate between the transistors formed above the substrate.
The gate electrode 14 has a critical dimension 12, i.e., the width of the gate electrode 14, that approximately corresponds to the channel length 13 of the device when the transistor 10 is operational. Of course, the critical dimension 12 of the gate electrode 14 is but one example of a feature that must be formed very accurately in modern semiconductor manufacturing operations. Other examples include, but are not limited to, conductive lines, openings in insulating layers to allow subsequent formation of a conductive interconnection, i.e., a conductive line or contact, therein, etc.
In the process of forming integrated circuit devices, millions of transistors, such as the illustrative transistor 10 depicted in FIG. 1, are formed above a semiconducting substrate. In general, semiconductor manufacturing operations involve, among other things, the formation of layers of various materials, e.g., polysilicon, insulating materials, etc., and the selective removal of portions of those layers by performing known photolithographic and etching techniques. These processes are continued until such time as the integrated circuit device is complete. Other processes are also involved, such as ion implantation and various heating processes.
During the course of fabricating such integrated circuit devices, a variety of features, e.g., gate electrodes, conductive lines, openings in layers of insulating material, etc., are formed to very precisely controlled dimensions. Such dimensions are sometimes referred to to as the critical dimension (CD) of the feature. It is very important in modern semiconductor processing that features be formed as accurately as possible due to the reduced size of those features in such modern devices. For example, gate electrodes may now be patterned to a width 12 that is approximately 120 nm (1200 Å), and further reductions are planned in the future. As stated previously, the width 12 of the gate electrode 14 corresponds approximately the channel length 13 of the transistor 10 when it is operational. Thus, even slight variations in the actual dimension of the feature as fabricated may adversely affect device performance. Thus, there is a great desire for methods that may be used to accurately, reliably and repeatedly form features to their desired critical dimension, i.e., to form the gate electrode 14 to its desired critical dimension 12.
In some cases, it is also desirable that the thickness of various process layers be very tightly controlled. Such layers may be formed by a variety of deposition processes, e.g., plasma enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD), sputter deposition, etc. Thermal growth processes may also be employed in manufacturing process layers. As one specific example, the thickness of the gate insulation layer 16 for the transistor 10 must be very tightly controlled to insure that the completed device meets strict performance requirements. As another example, the thickness of a barrier metal layer formed in an opening in an insulating layer must be precisely controlled to insure substantial coverage of the interior surfaces of the opening. Moreover, the thickness of the barrier metal layer needs to be relatively uniform to insure that it performs its intended function and to insure that it does not create additional problems for processes that are to be subsequently performed, e.g., filling the opening with a conductive material such as copper. Accurate placement of and implant regions of the appropriate depth and dopant concentration levels is also an important aspect of manufacturing modern integrated circuit devices.
Manufacturers of high performance integrated circuit products expend great effort in attempting to insure that the products meet the very stringent manufacturing tolerances. More particularly, a vast amount of metrology data is typically acquired at various points during the manufacture of the products. Typically, manufacturers often establish a standard metrology sampling protocol or pattern to acquire metrology data about the devices as they are being manufactured. For example, a typical sampling plan may involve collecting metrology data on every tenth lot of substrates that are processed. Within each of the sampled lots, a set number of substrates, e.g., four, may be subjected to metrology testing. Standard metrology sampling plans are also applied to each sampled wafer. For example, thickness measurements of a deposited layer of material may be taken at a preselected standard number of locations. The pattern of the metrology sites in such a standard sampling protocol are selected so as to attempt to obtain information reflective of the entire deposited layer.
Metrology data is also collected with respect to various aspects of photolithography processes performed in manufacturing semiconductor devices. A stepper exposure process typically involves exposing a layer of photoresist to a light source to establish a pattern in the layer of photoresist. Such stepper exposure processes are performed on a flash-by-flash basis as the substrate is moved, or stepped, relative to the light source. Each flash may expose an area, i.e., an exposure field, that covers a plurality of die, e.g., four die (a 2×2 exposure field). The number of exposure fields per substrate may vary depending on the size of the substrate, the number of die, and the size of the exposure field. For an illustrative substrate having 200-500 die, a stepper process using a 2×2 exposure field pattern (four die per exposure field), there will be between 50-125 exposure fields per substrate. However, a typical metrology sampling plan may involve obtaining metrology data from only one metrology site within each of nine exposure fields on the substrate.
The standard metrology sampling routines applied in modern semiconductor manufacturing are useful, but they do not provide sufficient information in a timely manner to avoid some manufacturing problems. What is desired are methods for acquiring metrology data that will, in some cases, provide more effective and useful data such that yields of acceptable products are increased while reducing rework and the consumption of scarce metrology tools and technicians. Moreover, metrology sampling needs to be more responsive so that problems and variations with tools and/or processes may be more quickly identified and corrected.
The present invention is directed to various methods and systems that may solve, or at least reduce, some or all of the aforementioned problems.